In integrated semiconductor circuits, a conductive connection is produced by means of contacts between the active components and the interconnects which are located in different structure levels. Integrated semiconductor circuits are in this case generally produced by means of a planar technique. This includes a sequence of individual processes which each act over the entire area of the surface of the semiconductor wafer and, by means of suitable masking layers, lead deliberately to local changes in the semiconductor material.
In this case, the semiconductor wafers are virtually always structured using lithography. The major feature of this technique is a radiation-sensitive photoresist, which is applied to the semiconductor wafer and is irradiated in the desired areas, such that only the irradiated or unirradiated areas are removed in a suitable developer. The photoresist pattern that is produced in this way is then used as a mask for a subsequent process step, for example contact hole etching. The photoresist mask is then dissolved once again.
The major driver for the development of integrated semiconductor circuits is the continuous miniaturization of the components, and thus also of the contact structures. The minimal extent of the contacts is in this case of critical importance to the efficiency with which the area of an integrated semiconductor circuit is used. The smaller the minimum separation between the individual contacts, the better can the available area on the semiconductor wafer be used. In order to make it possible to produce ever smaller structures and, in particular, contacts as well in the course of the progress of miniaturization, the planar technique offers the capability to change to shorter exposure wavelengths in the lithography process for exposure of the mask, in order to transfer the desired structures to the photoresist that has been applied to the semiconductor wafer. However, for financial reasons, it is at the same time desirable to continue to use the lithography equipment which exists at the moment for as long as possible, before the next shorter wavelength is used in order to achieve further structural size reductions.
In order to achieve reductions in structural size even with the present exposure wavelength, so-called resolution enhancement techniques (RET) are therefore increasingly being used for exposure. Off-axis illumination is particularly suitable for the formation of very small contact structures. In the case of off-axis illumination, the light source of the optical exposure device is not imaged centrally on the object opening, but obliquely, for example in an annular shape, by means of a fly's-eye lens or by means of a quadrupole lens. This off-axis illumination results in higher diffraction orders entering the objective openings, thus increasing the resolution.
During the production of integrated semiconductor circuits, in particular memory circuits, RET methods can in general be used to improve the resolution of contact structures only in the cell array area in which the contact structures have a regular pattern so that, for example, diffraction orders which improve the resolution are achieved by means of the off-axis illumination. However, in the logic area, the contact structures are generally not arranged regularly but have a high degree of complexity, on the one hand with contacts some of which are isolated from one another, and on the other hand with densely packed contacts. Since, in general, no RET methods can be used to form a structure of a reduced size in the logic area for this reason, semiconductor memory circuits generally need to have a greater separation between the contacts in the logic area than in the active area, thus leading to a deterioration in the utilization of the area.